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T-Hub’s new programme to boost semiconductor startups

New Delhi, Aug 16 (IANS) India’s largest expertise incubator T-Hub on Tuesday launched the semiconductor cohort of the AIC T-Hub Foundation programme to foster innovation and entrepreneurship throughout the semiconductor sector startups.

The programme will assist entrepreneurs navigate the challenges of scaling the startup by way of expert-led workshops, specialised mentorship, market entry, and investor and business connections.

“Indian engineers have contributed massively to the semiconductor sector whereas working with world corporations. Therefore, we should assist them in establishing and scaling their design startups with strong help from the ecosystem,”AMSR, CEO of T-Hub, stated in a press release.

“T-Hub and AIC, along with different ecosystem enablers by way of this program, try to present the semiconductor startups entry to the correct mentorship, funding channels and networking alternatives,” MSR added.

This is a six-month-long intense hybrid cohort-based programme that may mentor 20 startups with probably disruptive applied sciences that might reshape semiconductor provide chains sooner or later.

The startups shall be chosen based mostly on technological innovation, go-to-market readiness, scalability, and group composition. Interested startups can apply right here, and the appliance deadline is September 5.

The semiconductor cohort of the programme will make sure that the chosen startups get customised session for product commercialisation and market entry with the assistance of world mentors from the business.

T-Hub and AIM will assist the startups achieve authorities connections with Indian Semiconductor Mission (ISM), Semiconductor Complex and GAETEC (Galium Arsenide Technology Centre) for fast compliance, certification, and testing to go to market seamlessly.

T-Hub companions just like the Central Institute of Tool Design (CITD) and Qualcomm will present startups free entry to Electronic Design Automation (EDA) software program instruments for Very Large Scale Integration (VLSI) entrance and back-end improvement and analysis platforms to design, validate, and simulate fabless designs.

(Except for the headline, the remainder of this IANS article is un-edited)

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